Setup and Walk-through#
Obtaining and Running the Code#
In this homework, we will first run a matrix multiplication function on the cpu and then run the same matrix multiplication function on the FPGA.
Pull in the latest changes using:
cd ese532_code/
git pull origin master
The code you will use for this section
is in the hw6
directory. The directory structure looks like this:
hw6/
apps/
mmult/
cpu/
Host.cpp
fpga/
hls/
MMult.cpp
MMult.h
testbench.cpp
Host.cpp
design.cfg
package.cfg
xrt.ini
sourceMe.sh
common/
...
Useful Resources#
In this HW, we will analyze how the processor core communicates with an accelerator. We tell you some specific things to experiment with, but you should do some reading from:
This HW is highly related to this Vitis Host Code Optimization Tutorial
The following resources can be helpful for programming HLS and OpenCL host code:
Note that we are running on Linux. If you want to gain a deeper understanding of what’s going on under the hood and how the zocl driver supplied by Xilinx Runtime (XRT) manages DMA, refer to the following resources:
Building HW6#
Like we did in HW5,
source sourceMe.sh
first. Note that you need to adjust thesourceMe.sh
if you are running on your local machine. To build the cpu version of mmult, runmake cpu
, which produces themmult_cpu
executable. To build the FPGA kernel and the host code, runmake fpga
(this will take >30min). This will create the files that you need to copy over to the ultra96 inpackage/sd_card/
. To only build/rebuild the host code, runmake host
.
Like we did in HW5, copy the related files in
package/sd_card
directory to Ultra96’s/media/sd-mmcblk0p1/
and typereboot
. Enable the ethernet connection usingifconfig
. Next,scp
the.elf
file generated from CPU version.